Q: What is the difference between a Verilog task and a Verilog function?
A:The following rules distinguish tasks from functions:
· A function shall execute in one simulation time unit;
a task can contain time-controlling statements.
· A function cannot enable a task;
a task can enable other tasks or functions.
· A function shall have at least one input type argument
and shall not have an output or inout type argument;
a task can have zero or more arguments of any type.
· A function shall return a single value;
a task shall not return a value.
Q: What is the difference between the following two lines of Verilog code?
#5 a = b;
a = #5 b;
A: #5 a = b; Wait five time units before doing the action for "a = b;".
The value assigned to a will be the value of b 5 time units hence.
a = #5 b; The value of b is calculated and stored in an internal temp register.
After five time units, assign this stored value to a.
Q: What is the difference between:
c = d ? a : b;
and
if (d) c = a;
else c = b;
A:The ? merges answers if the condition is "x",
so for instance if c is 2 bit data, d = 1'bx , a = 2'b10, and b = 2'b11,
you'd get c = 2'bx.
On the other hand, in the 2nd condition if d=1, then c=a,
and if d= X or Z or 0 , you'd always get c =b.
Q: What is the difference between blocking and non blocking statements?
Give some examples.
A: Blocking Statements: A blocking statement must be executed before the
execution of the statements that follow it in a sequential block. They will be
executed in the same seq order as they are entered. = is used.
Nonblocking Statements: The nonblocking statements allows you to schedule
assignments without blocking the procedural flow. You can use the nonblocking
procedural statement whenever you want to make several register assignments
within the same time step without regard to order or dependence upon each
other. It means that nonblocking statements resembles the actual hardware
more then the Blocking assignments.
Example:
module block_nonblock();
reg a, b, c, d , e, f ;
// Blocking assignments
initial begin
a = #10 1'b1; // The simulator assigns 1 to a at time 10
b = #20 1'b0; // The simulator assigns 0 to b at time 30
c = #40 1'b1; // The simulator assigns 1 to c at time 70
end
// Nonblocking assignments
initial begin
d <= #10 1'b1; // The simulator assigns 1 to d at time 10
e <= #20 1'b0; // The simulator assigns 0 to e at time 20
f <= #40 1'b1; // The simulator assigns 1 to f at time 40
end
endmodule
Q. What is the difference between unary operators and binary operators in verilog?
Ans:- unary operators are used preceded to the operands where as the
binary operators are used in between the operands.
Q. What is the significance of defparam in verilog?
Ans: - Parameter values can be changed in any module instance in the
design with the keyword defparam. The hierarchical name of the module
instance can be used to override parameter values.
Q. Differance between Reduction and Bitwise operators?
Ans: - The difference is that bitwise operations are on bits from two
different operands,
whereas reduction operations are on the bits of the same operand.
Reduction operators work bit by bit from right to left.
Reduction operators perform a bitwise operation on a single vector
operand and yield a 1-bit result.
Bitwise operators perform a bit-by-bit operation on two operands.
They take each bit in one operand and perform the operation with
the corresponding bit in the other operand.
Q: Given the following Verilog code, what value of "a" is displayed?
always @(clk) begin
a = 0;
a <= 1;
$display(a);
end
A:This is a tricky one! Verilog scheduling semantics basically imply a
four-level deep queue for the current simulation time:
1: Active Events (blocking statements)
2: Inactive Events (#0 delays, etc)
3: Non-Blocking Assign Updates (non-blocking statements)
4: Monitor Events ($display, $monitor, etc).
Since the "a = 0" is an active event, it is scheduled into the 1st queue.
The "a <= 1" is a non-blocking event, so it's placed into the 3rd queue.
Finally, the display statement is placed into the 4th queue.
Only events in the active queue are completed this sim cycle,
so the "a= 0" happens, and then the display shows a = 0.
If we were to look at the value of a in the next sim cycle, it would show 1.
